Conventional voltage controlled power devices, such as IGBT or MOSFET, have been widely adopted in many power electronics equipment, such as motor drivers, inverters and switching mode power supplies. The reliability and performance of the power device is also heavily related on its gate driver circuit.
FIG. 1 illustrates an exemplary switch leg circuit with two IGBT devices (Q1 and Q2), which is a very popular structure adopted in many industry applications, such as motor drivers and inverters. In real application, the IGBT switch leg and DC input usually has some parasitic inductance Ls as indicated in FIG. 1. It may cause severe voltage overshoot across the switch during switching transient.
A conventional gate driver circuit is shown in FIG. 2. The gate drive signal is a pulse signal with required amplitude to drive the device. When the gate drive signal changes from VEE (negative amplitude) to VCC (positive amplitude), the device turns on; when the gate drive signal changes from VCC to VEE, the device turns off. Generally, VCC is around 12 to 18V and VEE is around 0V to −15V. The gate drive signal is applied to the gate emitter terminal of the device through the gate resistor Rg. The gate resistor is used to control the device (IGBT) switching behavior during switching transient, such as voltage/current change rate. IGBT turn on and turn off waveforms for an inductive load condition are shown in FIGS. 3A and 3B. Generally, the smaller the gate resistance, the faster the switching transient will be. In an inductive load condition, the load can be treated as a constant current source.
With continued to reference to FIGS. 1 and 3, the turn-on and turn off behavior of switch Q2 is further described although a similar explanation would apply to the behavior of switch Q1. Firstly, the turn on of the switch device is described. Before switch Q2 turns on, the load current freewheels through the internal diode D1 paralleled to switch Q1. At t0, the gate drive signal for switch Q2 changes from VEE to VCC to turn on switch Q2. The gate current is large at the beginning of turn on procedure but it decreases quickly as the voltage across resistor Rg decreases when VGe increases as shown in FIG. 3A. The current rising rate during [t1−t2] is depended by the gate current in this period (i.e., gate resistance). If the gate resistance is small, the current change rate is fast, which leads to a severe reverse recovery current of diode D1. There is a big current overshoot in the current through switch Q2. Also, excessive energy will be stored to the parasitic inductance existing in circuit, which will result in very high voltage overshoot across Q1/D1. Furthermore, the high reverse recovery current may lead to high EMI noise in the circuit. Therefore, it is necessary to limit this voltage overshoot and reverse recovery current. For the conventional gate drive, the only possible way to increase the gate resistance is to reduce the gate current. But the gate resistance affects the whole switching period. Thus, the turn on delay time td(on) and voltage falling time tfv will increase a lot too, which leads to high switching loss.
For turn off, at t0, the gate drive signal changes from VCC to VEE and switch Q2 starts to turn off. Similar to the turn on, the gate current decreases quickly when the gate voltage decreasing. The current fall rate during [t2−t3] will also induce a high voltage overshoot across switch Q2, which may cause device overvoltage and breakdown. It is necessary to limit this overvoltage for reliable operation. For the conventional gate driver, this can only be achieved by using a high value gate resistance, which also causes high switching loss since all the switching period is slowed. Therefore, how to effectively control the voltage/current overshoot while keeping the switching loss small is still a challenge for the gate driver circuit.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.